System synchronization clock specifications

10 MHz system reference clock: PXI_CLK10

Specification Value
Maximum slot-to-slot skew 1 ns
Accuracy ±25 ppm max (guaranteed over the operating temperature range)
Maximum jitter 5 ps RMS phase jitter (10 Hz to 1 MHz range)
Duty factor 45% to 55%
Unloaded signal swing 3.3 V ±0.3 V
NOTE:

For other specifications, see 'PXI-1 Hardware Specification' at the PXI Systems Alliance website (http://www.pxisa.org/userfiles/files/Specifications/PXIHWSPEC22.pdf).

100 MHz system reference clock: PXIe_CLK100 and PXIe_SYNC100

Specification Value
Maximum slot-to-slot skew 200 ps
Accuracy ±25 ppm max (guaranteed over the operating temperature range)
Maximum jitter 5 ps RMS phase jitter (10 Hz to 12 kHz range); 5 ps RMS phase jitter (12 kHz to 20 MHz range)
Duty factor for PXIe_CLK100 45% to 55%
Absolute single-ended voltage swing (when each line in the differential pair has 50 W termination to 1.30 V or Thévenin equivalent) 400 mV to 1,000 mV
NOTE:

For other specifications, see 'PXI-5 PXI Express Hardware Specification' at the PXI Systems Alliance website (http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF).

External 10 MHz reference out (SMA on front panel of chassis)

Specification Value
Accuracy ±25 ppm max (guaranteed over the operating temperature range)
Maximum jitter 5 ps RMS phase jitter (10 Hz to 1 MHz range)
Output amplitude 1 VPP ±20% square wave into 50 Ω 2 VPP unloaded
Output impedance 50 Ω ±5 Ω

External clock source

Specification Value
Frequency 10 MHz ±100 PPM
Input amplitude —
Front panel BNC 200 mVPP to 5 VPP square-wave or sine-wave
Front panel SMA input impedance 50 Ω ± 5 Ω